Field Programmable Gate Arrays (FPGA's) consist of configurable logic modules in rows and columns separated by channels for wiring. These devices are similar to gate arrays except that they contain segmented metal tracts that may be used for interconnection. The inputs of the logic modules of FPGAs are connected to dedicated vertical metal segments. Antifuses, or similar elements, are located at the intersection of the horizontal and vertical wire segments, and between adjacent horizontal and vertical wire segments. Am antifuse is programmed by applying a voltage across its terminal. A programmed antifuse provides a low resistance bidirectional connection between two segments. By choosing lengths of horizontal and vertical wire segments and the number of tracts in each channel, routing flexibility comparable to gate arrays can be achieved.
Wide input gate functions require a large number of logic modules to implement the desired function in prior art FPGAs. This is due to the fact that each logic module has a limited number of inputs. Multiple levels of logic modules are required in order to implement a function having more inputs than a single logic module because the outputs of several logic modules will need to be combined. Utilizing multiple levels introduces additional logic delays as well as requiring additional logic modules. Accordingly, a FPGA that can implement wide input gate functions more efficiently is desired.